The present invention relates to a complementary field effect transistor used for a high power integrated circuit (hereinafter referred to as "a power IC") and particularly to a complementary field effect transistor for power which is used for fabricating a power IC necessitating high current and high breakdown voltage, such as a power driver IC for DC motor.
The conventional complementary field effect transistor comprises an N-channel double-diffusion field effect transistor and a P-channel offset gate field effect transistor. Each of the N-channel double-diffusion field effect transistor 31 and the P-channel offset gate field effect transistor 32 is formed in either of the two well base regions which are formed with a given interval on a main surface of a semiconductor substrate. FIG. 1 is a cross section showing an example of a conventional complementary field effect transistor for power driver ICs. In FIG. 1, the N-channel double-diffusion field effect transistor (hereinafter referred to as "N-ch DMOS") comprises a base region 5, a source region 6 formed in the base region 5, a drain region 8, a high concentration drain region 7 formed in the drain region 8, and a first gate poly Si electrode (gate polycrystalline silicon electrode) 11 formed on the semiconductor substrate 20 between the high concentration drain region 7 and the source region 6 through a first gate insulating film 22. Further, in the N-ch DMOS, the base region 5 includes a high concentration base region 4 adjacent to the source region 6. The P-channel offset gate field effect transistor 32 (hereinafter referred to as "P-ch gate MOS") comprises a source region 13, a drain region 15, a high concentration drain region 16 formed in the drain region 15, an offset gate region 12a formed integrally with the drain region 15, and a P-channel gate poly Si electrode 19 formed on the semiconductor substrate 20 between the source region 13 and the high concentration drain region 16 through a second gate insulating film 23, wherein the P-channel gate poly Si electrode is formed in such a shape that a distance between an end of the P-channel gate poly Si electrode 19 and the high concentration drain region 16 is greater than a distance between the other end of the channel gate poly Si electrode 19 and the source region 13.
Further an N-channel source electrode 9 is provided on the source region 6, an N-channel drain electrode 10 is provided on the high concentration drain region 7, a P-channel source electrode 17 is provided on the source region 13, and a P-channel drain electrode 18 is provided on the high concentration drain region 16. Around the N-ch DMOS 31 and the P-ch offset gate MOS 32, a field insulating film 2 is provided, on which an interlayer insulator 21 is provided. Under the field insulating film 2, channel stoppers 3, 3, 3 are provided.
However, in the above conventional complementary field effect transistor, the offset gate structure is unavoidably applied with the present technical level in order to combine a high voltage N-channel transistor and an P-channel transistor into a complementary field effect transistor.
The offset gate region 12a provides a high breakdown voltage, whereas resistor components in the offset gate region 12a contributes to an on-resistance between drain and source. Therefore there is a limit in fabricating a P-channel transistor of low on-resistance. Further it is impossible to obtain short channel effect.
As above-mentioned, in the conventional complementary field effect transistor, P-channel transistor having both high breakdown voltage and low on-resistance cannot be formed. Therefore for implementing a driver IC for DC motor, it is necessary either to form a power transistor of only the N-ch DMOS 31 or to combine the N-ch DMOS 31 with the P-ch offset gate MOS 32. Therefore, in the former case, circuits become intricated, and switching time cannot be shortened above a fixed level. On the other hand, in the latter case, area of the P-ch offset gate MOS 32 becomes exceedingly larger than one of the N-ch DMOS. Therefore cost thereof increases.